IBM said Cell was "OS neutral" and would support multiple operating systems simultaneously but designers would not confirm if Microsoft's Windows was among those tested with the chip.
Translation: We aren't saying what architecture it is?
Blah, according to things I have read, cell in PS3 is supposed to make it connect to just about anything cell equiped... so you can use a cell toaster as your memory card lol.
well the PS2 performed good. I dont own an xbox but i like the PS2 better. Ive used an Xbox and im not saying there bad or anything but i like Ps better.
Blah, according to things I have read, cell in PS3 is supposed to make it connect to just about anything cell equiped... so you can use a cell toaster as your memory card lol.
Errrr ... no.
From what I know about Cell, it has nothing to do with interconnectivity between unrelated devices. It's just a parallel processor.
Cell cpu has been designed to work with other devices that is cell equipted, example.. a pda a computer and a printer all with cell chips, can be combined to work on a problem at the same time!!!
The Cell architecture is one of a PowerPC core and 8 specialized parallelized cores. The PPC core will deal with resource management and division of tasks between the 8 processing cores.
Each Cell contains 8 APUs. An APU is a self contained vector processor which acts independently from the others. They contain 128 X 128 bit registers, there are also 4 floating point units capable of 32 GigaFlops and 4 Integer units capable of 32 GOPS (Billions of Operations per Second). The APUs also include a small 128 Kilobyte local memory instead of a cache, there is also no virtual memory system used at runtime.
Clock speed over 4GHz.
100 GBytes per second aggregate Memory & I/O speed:
- Dual X D R controller gives 25.6 GBytes per second.
- Dual configurable interfaces give 76.8 GBytes per second.
8 X "SPEs", 128 bit vector engines, 128 registers each.
2 instructions issued per cycle per SPE.
Peak = 256 GigaFlops
Double precision maths operations supported.
256KBytes "Local Store" per SPE.
Internal communication is via 4 X 128 bit rings, up to 96 Bytes per cycle.
PPE can handle 2 threads (update: NOT POWER5 based).
PPE includes VMX.
PPE includes 512 KBytes Cache.
"Dynamic Power Management" technology.
Ten heat sensors
221 square mm in 90nm.
234 million transistors
90nm SOI, Low K, 8 layers of metal & Copper interconnect.
well the PS2 performed good. I dont own an xbox but i like the PS2 better. Ive used an Xbox and im not saying there bad or anything but i like Ps better.
Too many buttons in awkward places? Who the HELL needs *2* shoulder buttons? Really, the Xbox controller is a lot easier to use. But not the original, I'm talking about the S. The black/white buttons are too wierd on the original and the controller is too fricking huge.
Comments
Translation: We aren't saying what architecture it is?
-Q
-Q
PowerPC != Apple.
IBM makes the PowerPC, NOT Apple.
But where do a majority of PPC's end up?
-Q
-Q
Cell cpu has been designed to work with other devices that is cell equipted, example.. a pda a computer and a printer all with cell chips, can be combined to work on a problem at the same time!!!
Each Cell contains 8 APUs. An APU is a self contained vector processor which acts independently from the others. They contain 128 X 128 bit registers, there are also 4 floating point units capable of 32 GigaFlops and 4 Integer units capable of 32 GOPS (Billions of Operations per Second). The APUs also include a small 128 Kilobyte local memory instead of a cache, there is also no virtual memory system used at runtime.
100 GBytes per second aggregate Memory & I/O speed:
- Dual X D R controller gives 25.6 GBytes per second.
- Dual configurable interfaces give 76.8 GBytes per second.
8 X "SPEs", 128 bit vector engines, 128 registers each.
2 instructions issued per cycle per SPE.
Peak = 256 GigaFlops
Double precision maths operations supported.
256KBytes "Local Store" per SPE.
Internal communication is via 4 X 128 bit rings, up to 96 Bytes per cycle.
PPE can handle 2 threads (update: NOT POWER5 based).
PPE includes VMX.
PPE includes 512 KBytes Cache.
"Dynamic Power Management" technology.
Ten heat sensors
221 square mm in 90nm.
234 million transistors
90nm SOI, Low K, 8 layers of metal & Copper interconnect.
[Edit by Q: Fixed sidescrolling]
enjoy the reading.... if you want more let me know
I reallt thought it was.... is you want to do research look at ibm's website search for "sti cell" I really can not find too much from them
Why?